Apparatus and method for clock signal synchronization in JTAG testing in systems having selectable modules processing data signals at different rates

ABSTRACT

In a test and debug system in which a plurality of selectable modules under test have different operational rates, a selection unit associated with each module is used to control the application of the RCLK signal from the module to the adder unit, the adder unit providing a composite RCLK signal. Each selection unit has output signals of RCLK_NE and RCLK_PE signals which are applied to an adder unit to form the composite RCLK signal. In response to the SELECT signal, the RCLK_NE and RCLK_PE are synchronized with the module RCLK signal. When the SELECT signal is removed, the RCLK_NE and RCLK_PE signals are continuously applied to the adder unit. it.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to the application of a system clock to a plurality of selectable modules that process the clock signals at different rates. In particular, the modules process test and debug signals, such as JTAG signals, at different clock rates.

2. Background of the Invention

In certain processing units, different modules can process input signals at different clock rates. For example, modules of certain ARM Corporation processing units process test and debug signals at different rates depending on the module. In the JTAG test and debug format, not only is a clock (CLK) signal required, but a return clock (RCKL) signal must be present.

Referring to FIG. 1, a system having a plurality of modules processing data groups at different rates is illustrated. The processing system includes modules 1-N. Each module has a (system) CLK signal applied to an input terminal thereof. Each module processes data at a rate that is module-dependent. When the processing of the data is complete, the modules generate RCKL(l) through RCKL(N) signals. In FIG. 1, the application of test data in TDI(1) through test data in TDI(N) to the modules is illustrated. After processing, the test data out TDO(1) through test data out TDO(N) is retrieved from the modules. In the important JTAG example, the TDI(1) through the TDI(N) are applied, by means of a chain configuration, to the modules and the TDO(1) and TDO(N) are retrieved series format from the modules through a chain configuration. Consequently, it is necessary that the system clock signal be consistent with any of the RCLK(h) signals. Expressed in another manner, the TDI(k) are entered in the module, processed during a period of time determined by the design of the module, and retrieved from the modules for analysis.

As will be clear, either through failure of the system clock or as a result of variations in the time to process the data signals entered into each module, a timing error will occur.

In a typical test procedure, not all of the modules of the processing unit may be the subject of a particular test procedure. To include those modules might compromise the test procedure or reduce the speed with which the test and debug procedure can be performed.

It is therefore a feature of the apparatus and associated method to perform a test and debug procedure on selected modules of a processing system. It is yet another feature of the apparatus and associated method to determine when a return clock signal is not consistent with system clock signal during a test and debug procedure of processing unit having selectable modules. It is a more particular feature of the apparatus and associated method to generate return clock negative edge and positive edge signals for use in generating a composite RCL signal. It is yet another particular feature of the apparatus and associated method to apply RCLK_NE and RCLK_PE signals from selected modules to an adder circuit, the RCLK_NE and RCLK_PE signals being synchronized with the module RCLK signal. It is still a further feature of the present invention to apply RCKL_NE and RCLK_PE signals continuously to the adder unit for the deselected modules. It is yet another particular feature of the present invention to provide a seamless transition between the selection and the deselection of a module.

SUMMARY OF THE INVENTION

The aforementioned and other features are accomplished, according to the present invention, by providing each module with a selection unit. In response to a SELECT signal, the selection unit will provide a RCLK_PE (RCLK POSITIVE EDGE) signal and a RCLK_NE (RCLK NEGATIVE CLOCK) signal to an adder circuit, the RCLK_PE signals and the RCLK_NE signals being synchronized with the RCLK signal from the associated module. The RCLK_NE and RCLK_PE signals from the selected modules are combined to form a composite RCLK signal. For those modules for which the SELECTION signal is not applied, the RCLK_NE and RCLK_PE signals are continually applied to the adder unit. Because the RCLK_NE and the RCLK_PE signals from the non-selected modules are continuously applied to the adder unit, these signals do not participate in the generation of the composite RCLK signal, only the selected modules contribute to the formation of the composite RCLK signal. Therefore, only the selected modules contribute to the composite RCLK signal. The composite RCLK signal is compared with the CLK signal to identify timing problems in the (selected) modules.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a system having a plurality of modules processing data signals at different rates according to the prior art.

FIG. 2 is a block diagram for generating a composite RCLK signal for a system having a plurality of modules processing data signals at different rates according to the present invention.

FIG. 3 illustrates the waveforms generated by the circuit of FIG. 2.

FIG. 4 is a circuit diagram showing an implementation of an adder unit circuits for generating a RCLK signal suitable for use in FIG. 2.

FIG. 5 is a block diagram of a test and debug system with selectable modules according to the present invention.

FIG. 6 is a schematic diagram of the selection circuit associated with each module according to the present invention.

FIG. 7 is a schematic diagram of the adder unit when POSITIVE EDGE and NEGATIVE EDGE signals re applied to the adder unit according to the present invention.

FIG. 8 illustrates the waveforms in the selection unit of FIG. 6 when the SELECT signal is applied according to the present invention.

FIG. 9 illustrates the waveforms in the selection unit of FIG. 6 when the SELECT signal is removed according to the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT 1. Detailed Description of the Figures

FIG. 1 has been described with respect to the Related Art.

Referring to FIG. 2, a block diagram of the present invention is shown. As in FIG. 1, module 1 through module N process input data signals TDI(1) through TDI(N), respectively, at different processing rates. In the preferred embodiment, the TDI(1) through TDI(N) are shifted into the modules through a serial path. After processing, the output data signals TDO(1)-TDO(N) from the modules 1-N are transmitted to a host processing unit of analysis. A system clock CLK signal is applied to each of the modules 1-N. Each module 1-N also receives a clock signal CLK_FO-CLK_FN. The RCLK(1) through RCLK(N) signals from the modules 1-N are applied to adder circuit 20. The output signal from the adder circuit 20 is a composite RCLK signal.

Referring to FIG. 3, the technique for providing a composite RCLK signal from a plurality of RCLK(k) signals is illustrated. In FIG. 4, two RCLK signals RCLK0 and RCLK1 are used to illustrate how the RCLK signals are combined. The composite RCLK signal does not achieve a logic value until each of the component RCLK0 and RCLK1 signals have achieved this value. The logic signal in maintained or latched until both the RCLK0 and the RCLK1 signals have both obtained the complementary logic state. At this time, the composite RCLK signal changes to the complementary logic value. The complementary logic value in maintained until the component RCLK0 and RCLK1 both have returned to the return to the original logic state.

Referring to FIG. 4, an implementation of the adder circuit 20 of FIG. 2, providing the waveforms sown in FIG. 3, is shown. In the example of FIG. 4, four modules are assumed to be present. The RCLK(1) through RCLK(4) signal are applied to I of logic AND gate 41 and these same signals are applied to inverting terminals of logic AND put terminals of logic AND gate 42. The output terminal of logic AND gate 41 is applied to the T terminal of DQ flip-flop 43. The output terminal of logic AND gate 44 is coupled to the T terminal of DQ flip-flop 43. A POR (Power On Reset) signal is applied to the R terminals of logic ADD gate 43 and to the R terminal of logic ADD gate 44. The Q′ terminal of DQ flip-flop 43 is applied to the D terminal of DQ flip-flop 43. The Q terminal of DQ flip-flop 43 is applied to the D terminal of DQ flip-flop 44 and to a first input terminal of exclusive OR gate 45. The Q terminal of DQ flip-flop 44. is applied to a second input terminal of exclusive OR gate 45. The output signal of exclusive OR gate. is transmitted through amplifier 46 to become the RTCLK signal. FIG. 4 also indicates that the CLK signal is the CLK signal for the modules 1 through 4.

Referring to FIG. 5, the block diagram shown in FIG. 2 has been modified to provide for selectable modules. In addition to the clock signals, the data stream must similarly be controlled. The TDO(k) from the k^(th) module must be prohibited from reaching the host processor when the k^(th) module is not selected. Each module k has switch Sk associated therewith. The switch Sk, when closed, applies clock CLK signal to the module k and applies the RCLK(k) to the adder 20. Each module k has a multiplexer 4 k associated therewith. Each multiplexer 4 k has the TDI(k) signal applied to one input terminal, the TDI(k) signal also being applied to an input terminal of module k. The second input terminal of multiplexer 4 k has the TDO(k) signal from module k applied thereto. The signals which activate the switches Sk also provide the control signals for the multiplexer 4 k. The clock signal CLK_Fk is also applied to module k. The output signals from the selection unit are applied to comparator 55. The comparator determines when the composite RCLK signal and the CLK signal are consistent.

Referring next to FIG. 6, the circuit for selecting a particular module x is shown. A select control signal is applied to the D terminal of DQ flip flop 61 and to a D terminal of DQ flip-flop 62. The CLK_B signal is applied to the clock terminal of DQ flip-flop 61 and to a first input terminal of logic OR gate 66. The Q terminal of DQ flip-flop 61 is applied to a second input terminal logic OR gate 66 to a first input terminal of logic AND gate 63. The Q terminal of DQ flip-flop 63 is applied to a second input terminal of logic AND gate 63. The output terminal of logic AND gate 63 is applied to a second input terminal of logic OR gate 64 and to a second input terminal of logic OR gate 65. The RCLKx signal is applied to the clock terminal of DQ flip-flop 62, to a first input terminal of logic OR gate 64 and to an inverting first terminal of logic OR gate 65. The output terminal of logic OR gate 66 provides the CLKx signal. The output terminal of logic OR gate 64 provides the RCLKX_PE (positive edge) signal, and the output terminal of logic OR gate 65 provides the RCLKx_NE (negative edge) signal.

Referring to FIG. 7, the circuit shown in FIG. 4 is redrawn showing the use of positive edge signals and negative edge signals of the RCLKX signals in order to activate the RCLK signals.

Referring to FIG. 8, the signals for the selection network shown in FIG. 6 are illustrated for the situation wherein the SELECT signal is applied thereto. When the SELECT signal is applied to the associated switch Sx, the RCLKx signal participates in generation of the composite RCLK signal. When the In FIG. 9 illustrates the waveforms of FIG. 6 when SELECT signal is removed, the module is deselected from influencing the generation of the composite RCLK signal from adder 20.

2. Operation of the Preferred Embodiment

The operation of the present invention can be understood as follows. The comparison of an input clock signal with RCLK signals from a plurality of modules processing data signals at different rates can provide a method for determining an actual or potential malfunction in the test and debug procedure. In the present invention, modules in the system can be selected or deselected, i.e., each module can be selectively included in the test procedure. A selection unit is coupled to each module. A control signal is used to include the coupled module or not include the coupled module in the test procedure. When a module is selected, the RCLK_PE and RCLK_NE signals are synchronized with the positive and negative edges of the corresponding RCLK signal. The output signals from the selection unit are applied to the adder unit, the output of the adder unit being a composite RCLK signal for all of the selected modules.

When a module is not selected, i.e., the control signal is not applied, the selection unit provides continuous RCLK_PE and RCLK_NE signals to the adder unit. Because these signals are always present, the signals do not affect the output of the adder unit. Only the selected modules contribute to the composite RCLK signal.

In the comparator circuit, when the composite RCLK signal is and the system CLK signal have the same logic value, an ERROR signal is generated. This ERROR signal indicates, for example, that the test data in, TYDI, is entering a module before the test data out, TDO, have been retrieved from the module. Other malfunctions such as a system CLK malfunction can also be detected.

While the invention has been described with respect to the embodiments set forth above, the invention is not necessarily limited to these embodiments. Accordingly, other embodiments, variations and improvements not described herein are not necessarily excluded from the scope of the invention, the scope of the invention being defined by the following claims. 

1. In a test and debug system having a plurality of modules under test, a selection unit coupled to each module, the selection unit comprising: a first unit responsive to a system clock signal, a RCLK signal, and a SELECT signal, the first unit providing a GATE signal and a GATE_RET signal; and a second unit responsive to the GATE and the GATE_RET signal for generating a RCLK_PE signal and a RCLK_NE signal.
 2. The selection unit as recited in claim 1 wherein, in response to a SELECT signal, the RCLK_PE signal and the RCLK_NE are generated in synchronism with the RCLK signal.
 3. The selection unit as recited in claim 1 wherein, in the absence of the SELECT signal, the RCLK_NE and the RCLK_PE signal is generated continuously.
 4. The selection unit as recited in claim 1 wherein the test and debug system has a JTAG format.
 5. A method for applying a module RCKL signal to an adder unit to form a composite RCLK signal, the method comprising: applying a RCLk_NE signal and a RCLK_PE signal synchronized with the RCLK signal when a SELECT signal is applied; and applying a RCLK_NE signal and a RCLK PE signal continuously when a SELECT signal is not applied.
 6. The method as recited in claim 5 further comprising comparing the composite RCLK signal and the CLK signal.
 7. The method as recited in claim 6 further comprising generating an ERROR signal when the CLK signal and the RCLK signal have a preselected relationship.
 8. In a test and debug unit system, an apparatus for generating a composite RCLK signal, the apparatus comprising: A plurality of modules, each module processing data in signals at different rates; An adder unit; a selection unit coupled to each module, the selection unit having the RCLK signal from the coupled module applied thereto, the selection unit applying RCLK_PE and RCLK_NE signals synchronized with the RCLK signal to the adder unit when a control signal is applied to the selection unit, the selection unit applying continuous RCLK_PE and RCLK_NE signals to the adder unit when the first control signal is not applied to the selection unit; wherein the adder unit generates a composite RCLK signal for the selected modules.
 9. The apparatus as recited in claim 8 further comprising a comparator, the comparator comparing the CLK signal and the composite RCLK signal, the comparator generating an ERROR signal when the CLK signal and the RCLK signal have a preselected relationship.
 10. The apparatus as recited in claim 9 wherein the ERROR signal is generated when the composite RCLK signal transitions to the same logic state as the CLK signal. 